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multimedia video KS0125 page 1 of 36 introduction the KS0125 is a multistandard video encoder with line interpolation, crisping circuits, and on-screen-display (osd) functions. these special functions make this encoder well suited for mpeg playback applications, such as video compact disk (vcd), and digital video disk (dvd). features ? line interpolation ? crisping circuit to enhance horizontal resolution and to reduce mpeg mosquito effect ? 250 character rom containing the english and japanese alphabets, korean characters, numbers, and symbols. ? 4 user selectable osd character colors and 2 background colors ? ccir 601 or ccir 656 input ? ntsc-m or pal-b,g,h output ? master or slave timing operation with eav support for ccir 656 input ? adjustable hue ? 3 10-bit dacs for simultaneous cvbs and s-video output ? dacs support power-down mode ordering information device package operating temperature KS0125 80 - pqfp 0 to +70 c 80 - pqfp
KS0125 multimedia video page 2 of 36 block diagram color burst dac crisping m p interface clock circuit luma cvbs chroma xtli xtlo cko cki27 p[15:0] hsyn vsyn odd d[7:0] a0 cs r/ w int dac dac + x interpolation filter sync pulse lpf vertical filter y c osd generator osd ram timing generator f sc synthesizer interpolation filter
multimedia video KS0125 page 3 of 36 pin assignment- 80 pqfp 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 nc nc int vdd vss vdda vss nc nc cvbs nc vdda luma comp vss chroma p3 vss vdd p4 p5 p6 p7 p8 p9 p10 p11 p12 vss vdd p13 p14 KS0125 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n c c k i 2 7 r s t x t l i x t l o c k o v s s v d d n c n c n c n c n c n c n c n c v s s v d d o d d v s y n h s y n p 0 p 1 p 2 v s s n c i r e f v r e f v d d a n c v d d v s s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 v d d v s s v s s a 0 c s n c r / w p 1 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
KS0125 multimedia video page 4 of 36 typical application the KS0125 is shown in a typical vcd or dvd application figure 1. typical application vcd/dvd mpeg decoder KS0125 m controller ntsc/pal tv
multimedia video KS0125 page 5 of 36 pin cross reference: order by pin number pin # pin name pin # pin name pin # pin name pin # pin name 1 nc 21 hsyn 41 p15 61 vref 2 cki27 22 p0 42 r/ w 62 iref 3 rst 23 p1 43 nc 63 nc 4 xtli 24 p2 44 cs 64 vss 5 xtlo 25 p3 45 a0 65 chroma 6 cko 26 vss 46 vss 66 vss 7 vss 27 vdd 47 vss 67 comp 8 vdd 28 p4 48 vdd 68 luma 9 nc 29 p5 49 d0 69 vdda 10 nc 30 p6 50 d1 70 nc 11 nc 31 p7 51 d2 71 cvbs 12 nc 32 p8 52 d3 72 nc 13 nc 33 p9 53 d4 73 nc 14 nc 34 p10 54 d5 74 vss 15 nc 35 p11 55 d6 75 vdda 16 nc 36 p12 56 d7 76 vss 17 vss 37 vss 57 vss 77 vdd 18 vdd 38 vdd 58 vdd 78 int 19 odd 39 p13 59 nc 79 nc 20 vsyn 40 p14 60 vdda 80 nc
KS0125 multimedia video page 6 of 36 pin description pin name pin name i/o description digital video port p0 - p7 22 - 25, 28 - 31 i for ccir 601 data, these pins are the inputs for c0 - c7. for ccir 656 data, these pins are the inputs for yc0 - yc7. p8 - p15 32 - 36, 39 - 41 i these pins are for ccir 601 y0 - y7 inputs only. clock and timing xtli 4 i 13.5mhz crystal input, or 13.5 mhz cmos clock input. xtlo 5 o 13.5mhz crystal output. cki27 2 i 27mhz ttl clock input. cko 6 o 27mhz or 13.5mhz clock output(controlled by regc bit4). hsyn 21 i/o active low horizontal sync. it is an output in master mode; an input in slave mode(default). vsyn 20 i/o active low vertical sync. it is an output in master mode; an input in slave mode(default). odd 19 i/o field flag. high for field 1; low for field 2. it is an output in master mode; an input in slave mode. int 78 o open drain, active low interrupt. it is triggered by the start of the vertical sync. reset by software (vflg bit0). analog video output cvbs 71 o composite base band output(controlled by regd bit5). chroma 65 o chroma output(controlled by regd bit6). luma 68 o luma output(controlled by regd bit6). dac reference and compensation vref 61 - voltage reference. the chip contains a 1.235 v internal band gap reference. connect a 0.1 m f capacitor to vssa. iref 62 - current reference. a resistor with a nominal value of 787 w should be connected to this pin and ground. comp 67 - compensation capacitor for the dac internal reference amplifier. a 0.1 m f ceramic capacitor is required between this pin and ground. host interface a0 45 i address line. d0 - d7 49 - 56 i/o bidirectional data lines. cs 44 i chip select strobe for data read and write.
multimedia video KS0125 page 7 of 36 r/ w 42 i this pin controls the data flow direction when cs is low. a high indicates that the data is read from the chip. a low indicates the data is written to the chip. rst 3 i active low chip reset. power and ground vdd 8, 18, 27, 38, 48, 58, 77 +5v digital power supply. vdda 60, 69, 75 +5v analog power supply. vss 7, 17, 26, 37, 46, 47, 57, 66, 74, 76 gnd common ground. no connect nc 1, 9 - 16, 43, 59, 62, 63, 70, 72, 73, 79, 80 - these pins are reserved and should not be connected. pin description (continued) pin name pin name i/o description
KS0125 multimedia video page 8 of 36 functional description clock input and output the KS0125 requires an external clock for its operation. it also outputs a clock (cko) which can be used as a pixel clock for an external memory controller. clock input the KS0125 internally operates at 27 mhz. a 27 mhz ttl clock, a 13.5 mhz cmos clock or a 13.5 mhz crystal can be used to supply the internal clock. figure 4 shows the three possible external clock configurations. it is important that the unused clock input be grounded. the clock source should have no more than a 50 ppm frequency variation. figure 1. external clock configurations clock output the KS0125 provides an output clock (cko) which can be used as a pixel clock. the frequency of the output clock can be either 27 mhz or 13.5 mhz, which is selected via the ckosl bit in the regc control register. figure 2 shows the internal logic for this output clock . figure 2. output clock generation logic using a crystal KS0125 4 5 13.5 mhz 22 pf 22 pf xtli xtlo using a 27 mhz clock 2 cki27 27 mhz ttl clock n. c. 4 5 2 KS0125 xtli xtlo cki27 using a 13.5 mhz clock 13.5 mhz cmos clock n. c. 4 5 2 KS0125 xtli xtlo cki27 x2 1/2 internal clock cki27 xtli cko ck o sl 1 0 2 4 6
multimedia video KS0125 page 9 of 36 reset the KS0125 has a master reset pin rst . this input is used to set the internal operation to a predefined state. during power up, the input on this pin must remain low until the power supply is stable. when the rst is low, all the control registers are set to their default values. video timing the KS0125 can operate in either master or slave timing mode. there are three bidirectional synchronization signals: hsyn , vsyn , and odd. in master mode, these three signals are outputs. in slave mode, the KS0125 synchronizes to externally generated hsyn , and vsyn or odd. for ccir 656 format, the KS0125 will synchronize to the embedded eav. master mode timing in master mode, the KS0125 generates three synchronization signals: hsyn , vsyn , and odd. depending on the field rate, the KS0125 generates different synchronization timings for 50 hz and 60 hz video. for 50 hz video, figure 1 shows the three synchronization signals during the vertical interval. for 60 hz video similar timing is shown in figure 7. depending on which field is active, the vsyn transitions are either aligned to the falling edge of hsyn , or in the middle of a video line. odd is always aligned to the falling edge of hsyn . figure 1. synchronization timings during vertical interval for 50 hz video vsyn odd hsyn odd hsyn 310 311 312 313 314 315 316 317 624 625 1 2 3 4 5 6 7 8 318 319 320 623 even field odd field vsyn cvbs cvbs
KS0125 multimedia video page 10 of 36 figure 1. synchronization signals during vertical interval for 60 hz video. figure 2 shows the line timing. note that the pulse width for hsyn is the same as the cvbs horizontal sync . figure 2. video line timing the active video input is synchronized to hsyn . to accommodate external data latency, the phase between the start of the active video input and the leading edge of hsyn can be adjusted via hav[2:0] in control register regd , and shfhav in control register rege . pixel data alignment for 16 bit and 8 bit inputs are shown in figure 3 and figure 10, respectively. vsyn odd hsyn odd hsyn 263 264 265 266 267 268 269 270 1 2 3 4 5 6 7 8 9 10 271 272 273 525 even field odd field vsyn cvbs cvbs hsyn 13.5 mhz 64t 864t (60 hz) 64t cvbs 585t (50 hz) 1t chip delay* + hav *: this is the total propagation delay from p[15:0] input to dac output (t pd + t dly ).
multimedia video KS0125 page 11 of 36 . figure 3. pixel data alignment for 16 bit input figure 4. pixel data alignment for 8 bit input the reference point for pixel data setup and hold time is different for 27 mhz and 13.5 mhz clock inputs for 8 bit input data. if the 27 mhz clock input is used, the reference point is the rising edge of the cki27 input. if the 13.5 mhz clock input is used, the reference point is the rising edge of the cko output. for ccir 601 input, the setup and hold time is always referenced to the rising edge of the clock input. slave mode timing in slave mode operation, the KS0125 synchronizes to externally generated timing signals, or eav timing reference codes embedded in the ccir 656 data stream. for ccir 601 input, the internal horizontal timing counter is synchronized to the leading edge of the hsyn input. the KS0125 assumes the first active pixel input starts 122 pixel clocks (13.5 mhz) after the leading edge of hsyn for ntsc, or 132 pixel clocks for pal. the line counter gets reset by the leading edge of vsyn . the internal field counter is synchronized to the leading edge of either vsyn or odd input. the programmable fld bit in the control hsyn 13.5 mhz cb 0 cr 0 cb 2 cr 2 p[7:0] cb 718 cr 718 64t 122t+hav offset (ntsc) 132t+hav offset (pal) 720t 16t-hav(ntsc) 12t-hav(pal) y 0 y 1 y 2 y 3 p[15:8] y 718 y 719 1t hsyn 27 mhz cb y cr y p[7:0] cb y cr y 64t 122t+hav offset (ntsc) 132t+hav offset (pal) 720t 16t-hav(ntsc) 12t-hav(pal) (cki27 or cko) 1t
KS0125 multimedia video page 12 of 36 register rege is used to select one of the two inputs for field synchronization. for ccir 656 input, synchronization is done through the eav timing codes embedded in the digital video stream. the eav bit in rege must be set to a 1. for 8-bit cbycr input without eav timing codes, the KS0125 synchronizes to the external timing signals. the eav bit in rege must be set to a 0. if the KS0125 is programmed to use vsyn and hsyn for identifying the odd field (the fld bit in rege is set to a 0), the timing shown in figure 11 must be met. if the falling edge of the vsyn falls outside of the window, the field is identified as an even field . figure 5. identifying field using hsyn and vsyn in slave mode hsyn 27 mhz 4t min vsyn line 1 4t min 3t max odd field window 1t
multimedia video KS0125 page 13 of 36 digital data path and signal processing luminance data path figure 6 shows the functional block diagram for the luminance path . figure 6. luminance processing unit the KS0125 has a field interpolation filter which is very useful for single field input sources, such as mpeg 1. for single field video sources, the KS0125 uses the input for the odd field without change. the even field is interpolated from the input. the interpolation filter employs a proprietary algorithm to create the even field which results in a smooth edge along diagonal and vertical directions. the vertical interpolation filter generates the current line output using the current and previous line inputs. figure 13 shows how interlaced video is displayed on a crt. the vertical interpolation filter generates a line using the lines above and below it in the other field. this requires that pixel data for the line below the interpolated line be the input when the interpolated line is generated. for example, if line 274 in figure 13 is the line being interpolated, pixel data used for video line 12 (line n in the field buffer) must be the current input (refer to figure 1 and figure 7 for video line definition) . figure 7. field interpolation input requirement crisping circuit crisp vfir yin gain and vertical interpolation filter offset conversion vfm cor[1:0] gamen gamma sync pulse osd luminance interpolation filter y/c delay ycdly pden yout 273 (319) 11 (7) 274 (320) 12 (8) 275 (321) interpolated original note: line numbers are shown for ntsc with pal in the parenthesis. field buffer line n line n+1 line n+2
KS0125 multimedia video page 14 of 36 the crisping circuit further improves video quality. the crisping circuit is designed to reduce mosquito effect in mpeg 1 video. the functional block diagram is shown in figure 8. it consists of a band separation circuit, a coring circuit, and a gamma correction rom. the y data is first separated into high and low frequency components. the high frequency component ? s low amplitude signals can optionally be suppressed by the coring circuit. the amplitude can be binary codes 1, 3, or 6, which is selected by programming the cor[1:0] bits in rega . an additional gamma rom can apply gamma correction to the high frequency component after the coring function. two selections are provided for gamma correction. one has large peaking ( gamma in rega is set to a 1); the other has small peaking ( gamma is set to a 0). the gamma correction can be disabled by programming the gamen bit in rega to a 0. finally, the high and low frequency components are recombined . figure 8. crisping circuit block diagram the luminance data is gain and offset adjusted so its output will be at the correct ntsc or pal level. the sync and osd are inserted after the gain and offset conversion stage. before going to the dac, the luminance data is interpolated to 27 mhz. this up sampling will simplify the external analog reconstruction filter. figure 9 shows the characteristic of the interpolation filter. an optional one pipe line delay is also included to compensate for any yc delay in the reconstruction filter yin yout hpf coring gamma lpf
multimedia video KS0125 page 15 of 36 . figure 9. luminance pixel interpolation filter characteristi c chrominance data path figure 10 is the functional block diagram for the chrominance data path . figure 10. chrominance data path the chrominance path also contains a field interpolation filter which serves the same purpose as the field interpolation filter in the luminance path. both luma and chroma field interpolation filters are controlled by the two register bits vfir and vfm . 0 2 4 6 8 10 12 x 10 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 1 2 3 4 5 6 x 10 6 -5 -4 -3 -2 -1 0 1 2 3 4 5 hz d b hz d b a. overall view b. pass band view vertical filter lpf interpolation filter interpolation filter gain adjust sin cos osd character and background color u v vfir vfm cbw[1:0] bgclr[1:0] chclr[1:0] color burst gate cbcr inter- polation
KS0125 multimedia video page 16 of 36 the chrominance data passes through a low pass filter whose bandwidth can be controlled via cbw[1:0] in rega . the bandwidth can be 1.1 mhz, 1.45 mhz, or 1.75 mhz. the cb/cr data is interpolated from 6.75 mhz to 13.5 mhz, and then gain adjusted. the cb/cr data is then demultiplexed to cb and cr paths. osd character and background colors are inserted into the cb and cr data paths. two background colors (blue and black) or transparent background can be selected through bgclr[1:0] , and four character colors (white, cyan, green, and magenta) can be selected via chclr[1:0] , both in regb . the color burst gate is inserted and the 13.5 mhz cb and cr data are up sampled to 27 mhz through an interpolation filter. finally, the two color difference components are quadrature modulated by an internally generated subcarrier. the overall frequency response of the chrominance path is shown in figure 11 . figure 11. chrominance path overall frequency response 0 1 2 3 4 5 6 x 10 6 -50 -40 -30 -20 -10 0 0 2 4 6 8 10 12 14 16 x 10 5 -6 -5 -4 -3 -2 -1 0 1 hz d b d b hz a. overall view b. pass band view cbw[1:0] = 00 or 11 cbw[1:0] = 01 cbw[1:0] = 10 cbw[1:0] = 00 or 11 cbw[1:0] = 01 cbw[1:0] = 10
multimedia video KS0125 page 17 of 36 on-screen-display (osd) the on screen display (osd) allows the user to overlay characters over the video. the desired characters and their positions are programmed on the display screen via the 8-bit micorprocessor interface. figure 15 shows a block diagram of the osd. the osd block consists of a character display buffer ram,a character-generation font rom,character location generation,character boundary location generation and osd shaping circuits. the timing generator pixel counter and line counter of the KS0125 generate controls to define the osd display area.the ram address defines where the character will be displayed. the ram data output acts as the pointer to select a particular character from the character font rom. the character location generator converts the 12-bit character font rom outputs to serial character streams, while the boundary location generator creates a boundary to surround the character. finally,the osd shaping circuits performs character color selection and background color selection. the osd cb,cr and y outputs are properly shaped by band-limited filters to reduce the ringing caused by the abrupt amplitude changes . figure 12. on screen display block diagram osd color selection and background color selection the osd supports four different colors for the character display and two different background colors. the color select ion for the character and the background and the background are controlled by the programmable regb control register . tables 1 and 2 describle the osd color selection and background color selection. notics that the user is recommended to choose the color white for the osd character, bacause the KS0125 creates less flicking effect at the character boundary when white is chosen. table 1. osd character color selection regb color selection comments bit(6:5) 00 white default, 80% intensity 01 cyan 80% intensity, 60% saturation 10 green 80% intensity, 60% saturation 11 meaenta 80% intensity, 60% saturation timing generator line count pixel count display buffer ram data address m i c r o p r o c e s s o r i n t e r f a c e character font rom boundary location generator character location generator color select character boundary osd chaping cr cb y
KS0125 multimedia video page 18 of 36 osd display area the osd display area is illustrated in figure 15-1. the starting and ending position in the horizontal direction are 176 and 786 in terms of pixel counts for both ntsc and pal. the starting and ending position in the vertical direction are 41 and 241 for ntsc, and 47. therefore, there are 200 scan lines for ntsc and 240 scan lines for pal. figure 13. on screen display area osd ram address the osd display area can fit in 25 characters in the horizontal direction and 10 characters in the vertical direction.the osd ram address is used to assign a location for a display character in the osd display area. table 3 describes the osd ram address and the character location mapping. notice that the osd ram addresses between the on-screen lines are not continuously incremented. instead, each on-screen line starts from address 32n in decimal, where n=0,1,2,....,9. when programming the osd, even though each osd display line can hold 25 charactors (character 0 to character 24), the user is recommended to program an empty space (address 0ae hex) for the last character for each osd display line. this will avoid missing pixels at the last character position. in other words, the 25th character for each osd line shall always be programmed as an empty space by using address 0ae for the osd font rom. table 2. osd background color selection regb background color selection comments bit(6:5) 0x white character background is the video 10 green video blanked 11 meaenta video blanked 4 1 ( ntsc) 4 1 ( pal) 241 ( ntsc) 287 ( pal) 176(ntsc) osd display 176(pla) 786(ntsc) 786(pla) 241(ntsc) 287(pla) 38(ntsc) 44(pla)
multimedia video KS0125 page 19 of 36 . osd font rom the osd font rom contains a total of 250 characters. these character addresses are continuously incremented from 0 to 250 in decimal, (or 000 to 0f9 in hexadecimal). addressing the osd font rom by the osd ram data the osd ram data is used as the character pointer to select a particular character from the osd font rom. each character in the osd font rom is designated to fit within a 10 x 12 dot matrix. the pointer only points to the top left corner bit of each character matrix. when a character is selected by the osd ram data during a display scan, the osd rom control circuitry will automatically generate all necessary addresses to go through all bit locations of the 10 x12 character matrix. table 26 shows the contents of the osd font rom,along with their address locations. osd character boundary during the on screen display,the boundary location generator generates a boundary to surround a character. the actual character size is 12 x 14 dot matrix. with the boundary surrounding a character, the character size becomes a 14 x 16 dot matrix. valid time to access the osd ram there are two way to access the osd ram. one of them is using it when vfig bit 7 is high. the other is using int(pin # 78), as follows. table 3. osd ram address description osd ram address (hexadecimal) character location on screen 000 - 018 on-screen line1, character 0 to character 24 020 - 038 on-screen line2, character 0 to character 24 040 - 058 on-screen line3, character 0 to character 24 060 - 078 on-screen line4, character 0 to character 24 080 - 098 on-screen line5, character 0 to character 24 0a0 - 0b8 on-screen line6, character 0 to character 24 0c0 - 0d8 on-screen line7, character 0 to character 24 0e0 - 0f8 on-screen line8, character 0 to character 24 100 - 118 on-screen line9, character 0 to character 24 120 - 138 on-screen line10, character 0 to character 24
KS0125 multimedia video page 20 of 36 when inten=1 figure 14. when inten=1, int =high vblk intrst int 241(ntsc) 38(ntsc) 287(pal) 44(pal) 241(ntsc) 38(ntsc) 284(pal) 44(pal)
multimedia video KS0125 page 21 of 36 table 4. font rom table font code font code font code font code font code font code font code font code 00 20 40 60 80 a0 c0 e0 01 21 41 61 81 a1 c1 e1 02 22 42 62 82 a2 c2 e2 03 23 43 63 83 a3 c3 e3 04 24 44 64 84 a4 c4 e4 05 25 45 65 85 a5 c5 e5 06 26 46 66 86 a6 c6 e6 07 27 47 67 87 a7 c7 e7 08 28 48 68 88 a8 c8 e8 09 29 49 69 89 a9 c9 e9 0a 2a 4a 6a 8a aa ca ea 0b 2b 4b 6b 8b ab cb eb 0c 2c 4c 6c 8c ac cc ec 0d 2d 4d 6d 8d ad cd ed 0e 2e 4e 6e 8e ae ce ee 0f 2f 4f 6f 8f af cf ef 10 30 50 70 90 b0 d0 f0 11 31 51 71 91 b1 d1 f1 12 32 52 72 92 b2 d2 f2 13 33 53 73 93 b3 d3 f3 14 34 54 74 94 b4 d4 f4 15 35 55 75 95 b5 d5 f5 16 36 56 76 96 b6 d6 f6 17 37 57 77 97 b7 d7 f7 18 38 58 78 98 b8 d8 f8 19 39 59 79 99 b9 d9 f9 1a 3a 5a 7a 9a ba da n/a fa 1b 3b 5b 7b 9b bb db n/a fb 1c 3c 5c 7c 9c bc dc n/a fc 1d 3d 5d 7d 9d bd dd n/a fd 1e 3e 5e 7e 9e be de n/a fe 1f 3f 5f 7f 9f bf df n/a ff
KS0125 multimedia video page 22 of 36 d/a converters the KS0125 contains three high speed current dacs. each dac can drive a 75 load. the three dacs operate at the 27 mhz clock rate. the voltage supply for the dac must be decoupled from the power supply for the digital circuitry on the chip. the voltage between the analog supply (vdda) and digital supply (vdd) must be maintained within one diode voltage drop (0.7 v). the dacs require two external 0.1 m f capacitors and one 787 w resistor connected as shown in figure 15. also shown in figure 15 is an optional reconstruction filter for the dac output to reduce sinx/x distortion . figure 15. typical dac configuration with optional reconstruction filter host interface the KS0125 uses a parallel host interface for programming the control registers and osd ram. the bus consists of one address line, eight data lines, one read/write (r/ w ) line, and one chip select ( cs ) line. to access the control registers, an index is first written to the index register (a0 = 0). then the data is read from or written to the data register (a0 = 1). figure 16 shows how data is written to control register regb (index 1) and how to read control register vflg (index 2). figure 16. control register write/read sequence + _ 180pf 1% 100 w 1% 100pf 1% 301 w 1% 1k 1k 75 w 75 w 10pf 1% 5.6 m h 5% video op amp (av = 2) vdda + 787 w KS0125 comp iref vref 61 62 67 0.1 m f 0.1 m f dac a0 r/ w cs d[7:0] 01 04 02 data index data index data
multimedia video KS0125 page 23 of 36 writing to the osd ram is done by first writing the row number to the index register (the number must be offset by hex 10 to indicate that data written to the data register is intended for osd ram). a burst of 1 to 25 bytes is then written to the data register. the data will be transferred sequentially into the osd ram for the particular row starting from the first column location. figure 17 provides an example of how to change the first three characters in the first row. note that the osd ram can only be written. figure 17. o sd ram write sequence for both control registers and osd ram, the number written to the index register remains unchanged until a new number is written to it. for osd ram write, the internal auto-increment pointer gets reset to 0 either after the 25th location is written, or the index register is written. a0 r/ w cs d[7:0] 10 font font font index data data data
KS0125 multimedia video page 24 of 36 detailed register description the KS0125 contains eight user programmable control registers and one osd ram selection register. table 2 is a register summary list. the following is a description of the bits in each register. the default value is followed by an asterisk (*). register bits with no specific functions are indicated by a dash ( - ). table 5. register summary index mnemonic power-on default description 00h rega 79h control register a. 01h regb 04h control register b. 02h vflg 02h/82h vertical blank status and int reset control. the msb is a read only vertical blank flag. 03h hue 00h hue control register. 04h regc 00h control register c. 05h regd 25h control register d. 06h reserved 07h reserved. 07h rege 00h control register e. 08h - 0fh reserved - reserved. should not be written to. 10h - ffh osdram - internally, only bit 4 of the 8-bit index register is decoded. if bit 4 is a 1, data written to the data register (a0 = 1) is sent to the osdram.
multimedia video KS0125 page 25 of 36 control register a index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h rega cbw1 cbw0 vfir crisp gamen gamma cor1 cor0 cor[1:0] luma coring selection. 00 no coring. 01 1 lsb coring.* 10 2 lsb coring. 11 3 lsb coring. gamma gamma correction selection. 0 small peaking.* 1 large peaking. gamen luma gamma correction enable. 0 gamma correction disabled. 1 gamma correction enabled.* crisp luma crisper function enable. 0 cripser function is disabled. 1 crisper function is enabled (recommended for mpeg video).* vfir vertical filter enable. 0 vertical filter is disabled. 1 vertical filter is enabled (recommended for mpeg video).* cbw[1:0] chroma low pass filter bandwidth selection. 00 or 11 low bandwidth. 01 medium bandwidth (preferred for most video formats).* 10 high bandwidth. note the default value for this rega register is 79h. during normal operation, users are recommended to program this register to 60h.
KS0125 multimedia video page 26 of 36 control register b index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h regb osd chclr1 chclr0 bgclr1 bgclr0 pden fmt1 fmt0 fmt[1:0] encoder output video format selection. 00 ntsc.* x1 pal-b,g,h. 10 reserved. pden ntsc pedestal insertion. 0 no pedestal (japan ntsc). 1 pedestal is inserted.* bgclr[1:0] osd background color selection. 0x transparent.* 10 blue. 11 black. chclr[1:0] osd character color selection. 00 white.* 01 cyan. 10 green. 11 magenta. osd osd enable. 0 osd is disabled.* 1 osd is enabled.
multimedia video KS0125 page 27 of 36 vertical blank status and int reset index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h vflg vblk - - - - - 1 intrst intrst int reset control. 0 leave int unchanged.* 1 force int to the high state. vblk vertical blank flag. this is a read only status bit. the state of this bit tracks the state of the vsyn pin except that this is active high. this bit can be polled by software; when it is high, the osd ram can be updated. hue control register index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03h hue hue7 hue6 hue5 hue4 hue3 hue2 hue1 hue0 hue[7:0] hue adjust. this number is unsigned. the nominal value is 0. the hue can be adjusted at a resolution of 1.40625 degrees.
KS0125 multimedia video page 28 of 36 control register c index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04h regc vfm - - ckosl infmt mode - - mode master/slave timing mode selection. 0 slave mode.* 1 master mode. infmt digital video input format selection. 0 input is ccir 601.* 1 input is ccir 656. ckosl cko clock output frequency selection. 0 cko frequency is 13.5 mhz.* 1 cko frequency is 27 mhz. this selection is not available if cki27 is the clock input. vfm vertical filter mode selection. 0 only even field is interpolated.* 1 both fields are interpolated.
multimedia video KS0125 page 29 of 36 control register d index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h regd - ycen cvbsen - - hav2 hav1 hav0 hav[2:0] master mode active video start control. the KS0125 expects the first active pixel to be 122 13.5 mhz clocks after the leading edge of the hsyn (for pal, the number is 132). the following offset, in number of 27 mhz clocks, provides additional phase shifts to compensate for any external data latency. shfhav is bit 4 of rege . 000 +11+shfhav. 001 +9+shfhav. 010 +7+shfhav. 011 +5+shfhav. 100 +3+shfhav. 101 +1+shfhav.* 110 -1+shfhav. 111 -3+shfhav. cvbsen cvbs dac control. 0 cvbs dac is disabled. 1 cvbs dac is enabled.* ycen luma and chroma dacs control. 0 luma and chroma dacs are disabled.* 1 luma and chroma dacs are enabled.
KS0125 multimedia video page 30 of 36 control register e index mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07h rege - - - shfhav eav fld ycdly ckill ckill color kill. 0 enable color.* 1 force output to be black and white. color burst is still inserted. ycdly luma path data delay control. 0 no delay.* 1 one 27 mhz clock delay. fld field identification in slave mode. 0 use vsyn and hsyn for field identification.* 1 use odd input. eav slave mode synchronization selection. 0 use hsyn , vsyn or odd inputs for synchronization.* 1 use eav for synchronization. shfhav one additional 27 mhz clock phase shift for the start of active pixel in master mode 0 no shift.* 1 one 27 mhz clock shift.
multimedia video KS0125 page 31 of 36 absolute maximum ratings notes: 1. .absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. applied voltage must be current limited to the specified range, and measured with respect to vss. 3. forcing voltage must be limited to the specified range. 4. current is specified as a conventional current, flowing into the device. recommended operating conditions characteristics symbol value units supply voltage (measured to vss) v dd -0.5 to + 7.0 v analog and digital supply voltage difference d v ad -0.7 to +0.7 v digital input applied voltage (2) ( measured to vss) v i -0.5 v digital input forced current (3,4) a i -100 to +100 ma digital output applied voltage (2) ( measured to vss) v o -0.5 to (v dd +0.5) v digital output forced current (3,4) a o -100 to +100 ma digital short circuit duration (single output high state to vss) tdsc 1 sec analog short circuit duration (single output to vss) ta sc infinite ambient operating temperature (case) t a -60 to + 130 c storage temperature t s -65 to + 150 c junction temperature t j -65 to +150 c vapor phase soldering (1 min.) tvsol 220 c lead soldering temperature (10 sec., 1/4 from pin) tsol 300 c characteristics symbol min typ max units supply voltage (measured to vss) v dd 4.75 5.0 5.25 v reference voltage v ref - 1.235 - v reference current i ref - 1.569 - ma analog output load r l - 75 - w ambient operating temperature, still air t a 0 - 70 c
KS0125 multimedia video page 32 of 36 electrical chracteristics characteristics symbol min typ max units supply total power supply current (digital plus analog, ckin=27mhz.) i dd - - 200 ma digital-to-analog converter dac resolution res 10 - - bits voltage reference (vref) output v ref 1.110 1.235 1.360 v dac gain factor k dac 10.31 10.85 11.39 - k dac imbalance between dacs k imbac - 5% - +5% - dac reference current (v ref =nominal) i ref - 1.569 - ma reference resistor (v ref =nominal) r ref - 787 - w blanking level output voltage (ntsc and pal modes) v blank - 0.300 - v video output compliance voltage v oc - 0.3 - 1.6 v total output load resistance r l - 75 - w analog output delay t dly - 32 - ns digital i/o characteristics digital input voltage, logic high, ttl compatible inputs. v ih 2.5 - v dd v digital input voltage, logic low, ttl compatible inputs v il v ss - 0.6 v digital input current, logic high (v in =4.0 v) i ih - 10 m a digital input current, logic low (v in =0.4 v) i il - - 10 m a digital output voltage, logic high (i oh = - 400 m a) v oh 2.4 - v dd v digital output voltage, logic low (i ol =3.2 ma) v ol v ss - 0.4 v digital video port timing digital video input setup time to rising edge of pixel clock t svid 5 - - ns digital video input hold time from rising edge of pixel clock t hvid 5 - - ns cki27 frequency variation* d cki27 - - 50 ppm xtli frequency variation* d xtli - - 50 ppm clock duty cycle (cki27, xtli)* d 40% 50% 60% -
multimedia video KS0125 page 33 of 36 figure 18. video port data setup and hold time pipeline delay from p[15:0] input to dac input* t pd - 41 - 27mhz periods clock input-to-output (cki27 or xtli to cko) delay (65 pf load)* t dlyclk - - 12 ns clock doubler short/long term jitter d ckdbl - - 1 ns host interface timing cs low t pwl cs 148 - - ns cs high t pwh cs 296 - - ns r/ w setup time to falling edge of cs t s r/ w 8 - - ns r/ w hold time from rising edge of cs t h r/ w 222 - - ns a0 setup time to falling edge of cs t s a 8 - - ns a0 hold time from falling edge of cs t ha 8 - - ns write mode data setup time to rising edge of cs t sd 8 - - ns write mode data hold time from rising edge of cs t hd 8 - - ns read mode delay from falling edge of cs to data valid t validd - - 75 ns read mode delay from rising edge of cs to data 3-state t 3-stated - - 10 ns *: these parameters are guaranteed by by design. electrical chracteristics (continued) characteristics symbol min typ max units t svid t hvid cki27,xtli,cko p[15:0], hsyn , vsyn ,odd
KS0125 multimedia video page 34 of 36 figure 19. cki27 to cko delay figure 20. xtli to cko delay figure 21. write protocol for the host interface cki27 cko t dlyck t dlyck xtli cko (13.5 mhz) cko (27 mhz) d ckdbl t pwl cs t pwh cs t sr/ w t hr/ w t sa t ha t sd t hd cs r/ w a0 d[7:0] index data index
multimedia video KS0125 page 35 of 36 figure 22. read protocol for the host interface t pwl cs t pwh cs t sr/ w t hr/ w t sa t ha t hd cs r/ w a0 d[7:0] data t validd t 3-stated index t sd index
KS0125 multimedia video page 36 of 36 video performance the KS0125 encoder meets the requirements listed in the table below when configured using the application circuit of figure 15. the test methods and test signals meets the requirements of ntc report no. 7or eia/tia-250. a tektronix tsg1001 programmable tv generator and a tektronix vm700a video measurement set are used for measurement verification. video performance characteristics test name symbol test waveform min typ max unit amplitude response versus frequency ampresp multiburst to 4.2 mhz - 0.25 - db p-p differential gain dg modulated staircase or ramp (ntc-7 composite) - 1.5 - % p-p differential phase dp modulated staircase or ramp (ntc-7 composite) - 1.0 - deg p-p chroma nonlinear gain distortion cnlg three-level chroma signal (ntc-7 combination) - 1.0 - ire chroma nonlinear phase distortion cnlp three-level chroma signal (ntc-7 combination) - 1.0 - deg chroma-to-luma intermodulation climd three-level chroma signal (ntc-7 combination) - 1 - ire chroma/luma gain equality clgi 12.5t modulated pulse (ntc-7 composite) ycdly=low - 102.5 - % chroma/luma delay inequality (analog filter delay excluded) cldi 12.5t modulated pulse (ntc-7 composite) ycdly=low - 5 - ns luma nonlinear distortion lnld 5-step unmodulated staircase - 2.5 - % noise level noise1 100% unmodulated ramp - - 61 - db rms noise level noise2 100% unmodulated ramp - - 72 - db rms chroma am noise camn red field, 500khz bandwidth - - 56 - db rms chroma pm noise cpmn red field, 500khz bandwidth - - 58 - db rms field time waveform distortion ftwd field square wave - 1.5 - ire p-p line time waveform distortion ltwd 18 m s 100 ire bar (ntc-7 composite) - 0.5 - ire p-p long time waveform distortion: lotwd 10% / 90% apl bounce initial peak overshoot 15 ire peak overshoot after 5 seconds 1.5 ire

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